1. Field of Invention
This invention relates to integrated circuit packages, and more particularly to the testing of the mechanical properties of various adhesive layers used to connect members of a flip chip integrated circuit package.
2. Description of Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit (i.e., chip) is typically secured within a protective semiconductor device package. Each I/O pad of the integrated circuit is then connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the integrated circuit to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB. Newer ball grid array ("BGA") device packages described below have solder balls for attachment to flat metal pads on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single integrated circuit increases, the number of signal lines which need to be connected to external devices also increase. The corresponding number of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of device packages and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. In addition, the lengths of signal lines from integrated circuit I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Controlled collapse chip connection (C4) is a well known method of attaching an integrated circuit directly to a substrate made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AlN). The C4 attachment method is commonly referred to as the "flip chip" method. The I/O pads of the integrated circuit are typically arranged in a two-dimensional array upon a "frontside" surface of the integrated circuit, and a corresponding set of bonding pads are formed upon an upper surface of the substrate. A solder "bump" is formed upon each of the I/O pads of the integrated circuit. During C4 attachment of the integrated circuit to the substrate, the integrated circuit is inverted and the solder bumps are placed in physical contact with the bonding pads of the substrate. The solder bumps are then heated long enough for the solder to reflow. When the solder cools, the I/O pads of the integrated circuit are electrically and mechanically coupled to the bonding pads of the substrate. After the integrated circuit is attached to the substrate, the region between the integrated circuit and the substrate is filled with an adhesive "underfill" material which encapsulates the C4 connections and provides other mechanical advantages.
Grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from integrated circuit I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
The BGA device package is an increasingly popular type of grid array device package. FIG. 1 is a cross-sectional view of a BGA device package 10 in current use. BGA device package 10 is one form of a "flip chip integrated circuit package". BGA device 10 includes an integrated circuit 12 mounted upon an upper surface of a larger package substrate 14. Substrate 14 may be made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide or aluminum nitride). Substrate 14 includes two sets of bonding pads: a first set on an upper surface adjacent to integrated circuit 12 and a second set arranged in a two-dimensional array across the underside surface. The I/O pads of integrated circuit 12 are connected to corresponding members of the first set of bonding pads using the C4 technique described above. Members of the second set of bonding pads function as device package terminals. Solder balls (not shown) attached to members of the second set of bonding pads allow device package 10 to be surface mounted to an ordinary PCB. Substrate 14 includes one or more layers of electrically conductive "traces" (i.e., signal lines) which connect respective members of the first and second sets of bonding pads.
During the C4 mounting of integrated circuit 12 upon substrate 14, solder bumps 16 formed on I/O pads of integrated circuit 12 are placed in physical contact with corresponding members of the first set of bonding pads of substrate 14 and heated long enough for the solder to reflow. When the solder cools, the I/O pads are electrically and mechanically coupled to the corresponding members of the first set of bonding pads. A layer of an adhesive underfill material 18 is then formed in the region between integrated circuit 12 and substrate 14.
The C4 underfill material is typically a thermosetting polymer (e.g., an epoxy resin) which is dispensed in liquid form and becomes substantially rigid (i.e., hardens) during a curing process (e.g., with time and/or elevated temperature). The liquid underfill material is dispensed along one or more sides of integrated circuit 12, and capillary action is relied upon to draw the liquid underfill material into the space between the underside of integrated circuit 12 and the corresponding portion of the upper surface of substrate 14. The underfill material may include suspended particles of a thermally conductive and electrically insulating material (e.g., silica). Once cured, the underfill material essentially interlocks the surfaces of integrated circuit 12 and substrate 14 surrounding the C4 connections, reducing the mechanical forces acting upon the solder bumps during temperature cycling. In addition, the underfill material encapsulates the C4 connections, protecting them from contaminants (e.g., moisture, electrically conductive particles, etc.) As a result, the reliabilities of the solder bump connections are substantially increased.
Following the C4 mounting process, a thermally-conductive heat spreader may be attached to a "backside" surface of integrated circuit 12. The heat spreader conducts heat energy away from integrated circuit 12 during operation. FIG. 2 is a cross-sectional view of a heat spreader 20 attached to the downward-facing backside surface of integrated circuit 12 by an adhesive thermal interface layer 22. Adhesive thermal interface layer 22 may be, for example, a layer of a thermosetting polymer (e.g., an epoxy resin) which is dispensed in liquid form and becomes substantially rigid during a curing process as described above. Adhesive thermal interface layer 22 typically includes particles of a thermally conductive material (e.g., silver, aluminum, boron nitride, etc.).
In order to perform their intended functions, adhesive layers 18 and 22 must remain mechanically locked to the surfaces of their adherents. FIGS. 3-5 will be used to describe several different types of testing performed to provide increased confidence that adhesive layers 18 and 22 will indeed retain this mechanically locked state over time. FIG. 3 is a cross-sectional view of BGA device package 10 of FIG. 1 undergoing tension testing in accordance with a technique in current use. A pull stud 24 is attached to the upward-facing backside surface of integrated circuit 12 by an adhesive layer 26. Adhesive layer 26 has a bonding strength greater than that of the layer of adhesive underfill material 18. Substrate 14 is held in place, and an upward vertical force F, normal to the upper surface of integrated circuit 12, is applied between pull stud 24 and substrate 14. Force F is increased until the layer of adhesive underfill material 18 fails and integrated circuit 12 separates from substrate 14. The maximum tensile force F endured by the layer of adhesive underfill material 18 prior to failure is compared to a predetermined minimum tensile force value. A maximum tensile force F equal to or exceeding the minimum tensile force value indicates long term reliability of the layer of adhesive underfill material 18.
FIG. 4 is a cross-sectional view of BGA device package 10 of FIG. 1 undergoing "peel" testing in accordance with a current technique. Substrate 14 is again held in place, and the beveled edge of a chisel blade 28 is brought into contact with the layer of adhesive underfill material 18. A lateral force F is applied along chisel blade 28 as shown in FIG. 4. Force F tends to cause the layer of adhesive underfill material 18 to pull up and away (i.e., "peel") from substrate 14. Force F is increased until the layer of adhesive underfill material 18 fails and integrated circuit 12 separates from substrate 14. The maximum "peel" force F endured by the layer of adhesive underfill material 18 prior to failure is compared to a predetermined minimum "peel" force value. A maximum "peel" force F equal to or exceeding the minimum "peel" force value indicates long term reliability of the layer of adhesive underfill material 18.
FIG. 5 is a cross-sectional view of BGA device package 10 of FIG. 1 undergoing "shear" testing in accordance with a current technique. Substrate 14 is again held in place, and a notch in a blade 32 of a "pusher" tool is brought into contact with the upper surface and one side of integrated circuit 12 as shown in FIG. 5. A lateral force F is applied along blade 32. Force F tends to cause the layer of adhesive underfill material 18 to separate from and slide over the upper surface of substrate 14. Force F is increased until the layer of adhesive underfill material 18 fails and integrated circuit 12 separates from substrate 14. The maximum "shear" force F endured by the layer of adhesive underfill material 18 prior to failure is compared to a predetermined minimum "shear" force value. A maximum "shear" force F equal to or exceeding the minimum "shear" force value indicates long term reliability of the layer of adhesive underfill material 18.
Disadvantages with the tension, peel, and shear tests shown in FIGS. 3, 4, and 5, respectively, include the time consuming setup steps required for each separate test. In addition, during the peel test in FIG. 4, a portion of force F transmitted from chisel blade 28 to integrated circuit 12 often results in cracks 30 occurring within the brittle semiconductor substrate material of integrated circuit 12. Similarly, during the shear test in FIG. 5, a portion of force F transmitted from blade 32 of the pusher tool to integrated circuit 12 often results in cracks 34 occurring within integrated circuit 12. Such cracks 30 and 34 cause the results of the test to be unreliable. Consequently, when cracks 30 or 34 occur within integrated circuit 12 during testing, the BGA device package 10 under test must be discarded, and the test must be repeated upon a new BGA device package 10.
It would be beneficial to have a single apparatus and associated method which allow either tension, peel, or shear testing to be performed upon various adhesive layers used to connect members of a flip chip integrated circuit package. Such an apparatus would apply a force between integrated circuit 12 and a second adherent (e.g., substrate 14 or heat spreader 20) such that integrated circuit 12 is not damaged during testing. Eliminating damage to integrated circuit 12 reduces the amount of time required to perform testing on a statistically meaningful number of flip chip integrated circuit packages.